1. Field of the Invention
The invention relates to analog-to-digital converters and, more particularly, to meters employing analog-to-digital converters for a plurality of alternating current power lines. The invention also relates to a method of analog-to-digital conversion and, more particularly, to such a method that synchronizes serially communicated output digital values from analog-to-digital conversions.
2. Background Information
Whenever there are serial streams of data for a plurality of different channels, synchronization of the data is an issue. A typical mechanism for resolving this issue is to employ dedicated hardware to provide a suitable synchronization signal. For example, if the starting point of a clock associated with one set of serial data for the different channels of an analog-to-digital (A/D) converter is known, then the dedicated hardware can be employed to assure synchronization (and, thus, provide a subsequent starting point) for a subsequent second set of data for those different channels. However, in the absence of such a synchronization signal, another mechanism is required.
It is known to provide an A/D converter having a plurality of input analog channels and a single addressable digital output.
Channel synchronization can apply to any count of plural channels. For example, FIG. 1 shows, for six channels, the relative timing of serial data including a serial enable (SE) input signal 2, a serial data output frame sync (SDOFS) output signal 4, and a serial data output (SDO) signal 6 from a six-channel, serial output A/D converter (not shown) for two successive sets 8,10 of six samples. Serial data is normally read from the A/D converter with simultaneously sampled channels appearing in consecutive order (i.e., samples 12,14,16,18,20,22 of the first set 8; samples 24,26,28,30,32,34 of the second set 10). This process is continuous until the sampling system of the A/D converter is reset or loses power.
Alternatively, some A/D converters output one SDOFS output signal for only the first of six samples.
However, other than the initial synchronization of the six channels via the SE input signal 2, there is no physical mechanism to verify that the sampled six channels are in the correct order (e.g., the correct samples 12,14,16,18,20,22 of one set, such as 8, versus, for example, samples 16,18,20,22 of one set, such as 8, erroneously combined with samples 24,26 of a subsequent set, such as 10) in the SDO signal 6. For example, if noise or another malfunction results in extra or missing SDOFS output signal(s) 4, then the hardware (not shown) downstream of the A/D converter (not shown) has no mechanism to detect this error. Hence, it is believed that only some hypothetical interpretation of the data (i.e., the samples 12,14,16,18,20,22 and/or the samples 24,26,28,30,32,34) from the SDO signal 6 might reveal whether the channel data is in the appropriate order for each of the sets 8,10 of samples.
There is room for improvement in analog-to-digital converters, meters employing analog-to-digital converters and methods of analog-to-digital conversion.